集成电路技术领域最新进展及新技术展望

目前,最先进的CMOS工艺逐渐逼近单原子尺度,单纯靠工艺进步来推动发展的时代即将结束,集成电路发展将进入"后摩尔时代"。在"后摩尔时代",集成电路的发展不会随着"摩尔定律"失效而终结,相反,以应用为导向的需求将使集成电路呈现出更加旺盛的发展活力。在边缘计算、人工智能、5G/物联网等应用需求快速兴起的背景下,从集成电路涉及的材料、器件、工艺、设计、封装、新理论及方法学等方面,详细介绍了"后摩尔时代"集成电路最新进展,分析其发展趋势。最后,简要介绍了未来可能对集成电路当前技术路线产生颠覆性影响的二维器件、量子计算等前沿领域的进展,并进行了展望。     

基于硬件实现的基因算法的研究

本文提出了一种VLSI实现的硬件基因算法.研究了基因算法的各种变种,探讨了它们的性能及硬件实现的可能性.提出了一个能进行群体存储、父本选择、交叉、变异等操作且易于硬件实现的结构.在硬件实现上,用VHDL描述了整个算法.所作的设计是一个通用的VLSI结构,通过流水线结构和并行化操作获得了很好的性能.硬件实现基因算法有效地缩短运行时间,为实时应用提供了可能.整个设计用Altera公司的FLEX10K40型号的芯片进行了FPGA实现,它完全可以用VLSI来实现.     

应用遗传算法进行低功耗状态编码

本文研究了用遗传算法进行有限状态机(FSM)的低功耗状态编码问题.基于FSM的概率模型,对编码空间进行并行搜索;通过在适应性度量中引入面积和状态翻转信息,实现了面积和功耗之间的折衷.对一些FSM的实际测试表明此方法平均能达到20%的功耗优化.     

基于RISC-V处理器的卷积加速SoC系统设计

为提高卷积神经网络（CNN）的计算效率和能效,以8 bit定点数据作为输入,设计一个支持激活、批标准化以及池化等CNN网络中常见计算类型的卷积加速器,优化循环计算顺序并将其与数据复用技术相结合,以提高卷积计算的效率。基于软硬件协同设计思想,构建包含RISC-V处理器和卷积加速器的SoC系统,RISC-V处理器基于开源的指令集标准,可以根据具体的设计需求扩展指令功能。将该SoC系统部署在Xilinx ZCU102开发板上,RISC-V处理器和卷积加速器分别工作在100 MHz和300 MHz频率下,测试结果表明,该加速器的算力达到153.6 GOP/s,运行VGG16网络进行图片推理计算时加速效果较好。     

基于Z参数的微波晶体管高频噪声网络分析方法

For high-capacity wavelength division multiplexing(WDM) in optical fiber transmission systems, multi-wavelength light sources are needed to be operated at precisely-determined wavelength swith a fine separation of 0.8 or 1.6nm.Increasing efforts have been put into deve...     

Circuit Design of On-Chip BP Learning Neural Network with Programmable Neuron Characteristics

A circuit system of on chip BP(Back-Propagation) learning neural network with pro grammable neurons has been designed,which comprises a feedforward network,an error backpropagation network and a weight updating circuit. It has the merits of simplicity,programmability, speedness,low power-consumption and high density. A novel neuron circuit with pro grammable parameters has been proposed. It generates not only the sigmoidal function but also its derivative. HSPICE simulations are done to a neuron circuit with level 47 transistor models as a standard 1.2tμm CMOS process. The results show that both functions are matched with their respec ive ideal functions very well. The non-linear partition problem is used to verify the operation of the network. The simulation result shows the superior performance of this BP neural network with on-chip learning.     

High Quality SiGe Layer Deposited by a New Ultrahigh Vacuum Chemical Vapor Deposition System

1. IntroductionBecause of the properties adjustable by the straindistribution and the possible integration with standard silicon technologyt silicon-germanium (SiGe)heterosystem has become more important in recentyears. A number of interesting electronic and optical devices based on it have been realized. Thesedevices include heterostructure field effect transistors(HFET)["'l, heterojunction bipolar transistors[3-5],and the infrared detectorsl6-8]. This prospect has encouraged the search fo…     

面向RF IC的片上铁氧体磁膜电感

采用集成工艺制作了片上铁氧体磁膜(Ni0.4Zn0.4Cu0.2Fe2O4,Y2.8Bi0.2Fe5O12和Co7ZrO9)射频微电感.铁氧体薄膜采用溶胶凝胶法制作,高频特性较好,适于片上电感的应用.对电感样品进行了测试和等效电路分析,结果表明,与无磁膜结构相对比,铁氧体磁膜电感显著增强了电感性能,是一种实现小尺寸、高性能片上RF IC电感的很有前景的途径.     

Implementation of AVS Jizhun decoder with HW/SW partitioning on a coarse-grained reconfigurable multimedia system

In this paper,a TPP(Task-based Parallelization and Pipelining)scheme is proposed to implement AVS(Audio Video coding Standard)video decoding algorithm on REMUS(REconfigurable MUltimedia System),which is a coarse-grained reconfigurable multimedia system.An AVS decoder has been implemented with the consideration of HW/SW optimized partitioning.Several parallel techniques,such as MB(Macro-Block)-based parallel and block-based parallel techniques,and several pipeline techniques,such as MB level pipeline and block level pipeline techniques are adopted by hardware implementation,for performance improvement of the AVS decoder.Also,most computation-intensive tasks in AVS video standards,such as MC(Motion Compensation),IP(Intra Prediction),IDCT(Inverse Discrete Cosine Transform),REC(REConstruct)and DF(Deblocking Filter),are performed in the two RPUs(Reconfigurable Processing Units),which are the major computing engines of REMUS.Owing to the proposed scheme,the decoder introduced here can support AVS JP(Jizhun Profile)1920×1088@39fps streams when exploiting a 200 MHz working frequency.